New Hardware Architecture Design for Intra Prediction in H.264/AVC High Profile

This paper analyzes intra prediction method in H.264/AVC high profile, and designs a reconfigurable hardware decoding architecture for intra prediction. To effectively reduce access times and resource consumption for on-chip RAM, an efficient buffer design is presented in prediction mode selection and reference pixel access. Based on the similarities of intra prediction for different modes, a reconfigurable computational module is designed to adapt to the 26 prediction modes in H.264/AVC so as to reduce chip area. To speed up intra prediction and make reconstruction more convenient, pre-processing for Plane mode and eight parallel processors are adopted in the proposed architecture. The proposed architecture is implemented by SMIC 0.18 um technology with about 55 K gate counts at 165 MHz. Experimental results show that the proposed architecture is capable of real-time decoding 1080i HD intra frame video sequences at 30 frames per second with H.264/AVC high profile.