DocumentCode
3350897
Title
Describing controlling hardware in VHDL
Author
Spillane, John ; Navabi, Zainalabedin
Author_Institution
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
37987
Abstract
A description style for synthesizable description of synchronous state machines with asynchronous control is presented. This style uses an implicit clock at an abstraction level convenient for hardware designers. High level behavioral constructs of VHDL including WAIT statements are allowed in this synthesis style. Hardware correspondence for all allowable constructs have been designed and complete examples have been implemented
Keywords
VLSI; application specific integrated circuits; finite state machines; logic CAD; specification languages; VHDL; WAIT statements; abstraction level; asynchronous control; controlling hardware description; description style; hardware designers; high level behavioral constructs; implicit clock; synchronous state machines; synthesizable description; Circuit synthesis; Clocks; Digital circuits; Hardware design languages; Process control; Process design; Production; Registers; Silicon compiler; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242933
Filename
242933
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