Test generation algorithms

Summary form only given. Test generation algorithms are algorithms used for computing the test sets for production testing ICs. In this tutorial the author discusses some of the `state of the art´ test generation algorithms for combinational circuits. This is not as restrictive as it first appears if one considers the fact that circuits are being designed using the `design for testability´ rules like LSSD etc. Such design for testability rules reduces the test generation problems for sequential circuits to that of its combinational components. The author discusses deterministic test generation algorithms for a variety of fault models like single stuck-at faults, FET stuck-open faults, delay faults, bridging faults as well as leakage faults