A generalized extraction system for VLSI

Author

Dukes, Michael A. ; Brown, Frank M. ; Degroat, Joanne E.

Author_Institution

Dept. of Electr. & Comput. Eng., Air Force Inst. of Technol., Wright-Patterson AFB, OH, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38200

Abstract

A generalized extraction system (GES) performs verification of circuits through logic extraction from transistor/component netlists, identification and location of logic errors within and between components, pin-to-pin critical path analysis, and generation of VHDL and ML. Extraction rules are automatically built from structural VHDL code. Logic extraction has been performed, on transistor netlists extracted from design layouts in magic, up to the level of 32-bit adders, 32-bit registers, and ALUs

Keywords

VLSI; application specific integrated circuits; circuit layout CAD; critical path analysis; digital integrated circuits; logic CAD; specification languages; 32-bit adders; 32-bit registers; ALUs; ASIC; ML generation; Meta language; VLSI; component netlists; design layouts; design verification; generalized extraction system; generation of VHDL; location of logic errors; logic errors identification; logic extraction; magic; pin-to-pin critical path analysis; structural VHDL code; transistor netlists; verification of circuits; Adders; Automatic logic units; Data mining; Integrated circuit interconnections; Logic circuits; Logic design; Military computing; Performance analysis; Registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242939

Filename

242939