A 20 MHz low power CMOS ASIC for a 1553 bus interface unit

Digital Technology Inc. has developed and is successfully marketing a 1553 Bus Interface Monitor Unit. However, a reduction in power consumption and area had to be pursued in order to make the system more efficient. This project deals with the design, simulation and testing results of an ASIC that will be part of a newly redesigned unit with a significant reduction in power and component count. To achieve this, CMOS and pseudo-NMOS technologies were used to replace the original TTL and PAL chips, respectively. The prototype chip was fabricated by MOSIS using a 2 μm CMOS N-well process and packaged in a 108-pin PGA having an area of 7.9×9.2 mm² and a power consumption of much less than 1 watt