Title :
Single-chip FIR adaptive filter using CMOS analog circuits
Author :
Gomez, Gabriel ; Siferd, Raymond
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
The design, simulation and testing results for a sampled-data analog adaptive filter are presented. The system uses clocked sampled-data storage, unique area-efficient analog multipliers, and other opamp-based arithmetic modules. The fully analog CMOS design features a non-multiplexed parallel architecture for achieving fast sampling rates and easy extension to higher order filters. The prototype chip was fabricated using 2-μ CMOS P-WELL technology, occupying an area of 4.0 mm2, and using ±5 V power supplies
Keywords :
CMOS integrated circuits; VLSI; adaptive filters; analogue processing circuits; application specific integrated circuits; multiplying circuits; 2 micron; 5 V; ASIC; CMOS; P-WELL technology; analog CMOS design; area; area-efficient analog multipliers; clocked sampled-data storage; fast sampling rates; non-multiplexed parallel architecture; opamp-based arithmetic modules; prototype chip; Adaptive filters; Analog circuits; Arithmetic; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Circuit testing; Clocks; Finite impulse response filter; Parallel architectures;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242948
