DocumentCode
3351118
Title
TUTCA configurable logic cell array architecture
Author
Korpiharju, Tapio ; Viitanen, Jouko ; Kiminkinen, Hannu ; Takala, Jarmo ; Kaski, Kimmo
Author_Institution
Dept. of Electr. Eng., Tampere Univ. of Technol., Finland
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38047
Abstract
A processor array architecture based on dynamically configurable logic cell array is designed to contain an 8×8 array of processing units. This array is expandable to construct larger arrays by combining chips together in a matrix. The configuration data for the processing units is loaded parallel into an internal configuration RAM to enable quick reconfiguration for a new task
Keywords
CMOS integrated circuits; VLSI; application specific integrated circuits; cellular arrays; parallel architectures; ASIC; TUTCA; configurable logic cell array architecture; configuration data; dynamic reconfiguration; dynamically configurable logic cell array; internal configuration RAM; processor array architecture; reconfigurable logic arrays; Computer architecture; Computer networks; Concurrent computing; Logic arrays; Logic circuits; Logic design; Parallel processing; Programmable logic arrays; Routing; Transmission line matrix methods;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242950
Filename
242950
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