A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function

Author

Roy, Subir ; Narayanan, H.

Author_Institution

Indian Inst. of Technol., Bombay, India

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38078

Abstract

An area efficient 2 level implementation of combinational logic can be achieved by partitioning the original PLA into several PLAs each of which interacts with the others weakly. A PLA implementing a sum of products logic functions can be modelled through a bipartite graph B _G, which specifies the intersection of rows (minterms) with columns of the AND plane (primary inputs) and the OR plane (primary outputs) respectively. The authors show how to achieve a good PLA partition by using the principal lattice of partitions of the incidence function of B_G

Keywords

VLSI; combinatorial circuits; graph theory; logic arrays; logic design; OR plane; PLA partitioning; bipartite graph; combinational logic; incidence function; minterms; partitions; primary inputs; principal lattice; submodular function; sum of products logic functions; Automata; Bipartite graph; Circuit synthesis; Erbium; Heuristic algorithms; Lattices; Logic functions; Programmable logic arrays; Size measurement; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242957

Filename

242957