DocumentCode
3351260
Title
A low power clock distribution scheme for complex IC system
Author
Ta, Paul D. ; Do, Kieu
Author_Institution
VLSI Technology Inc., San Jose, CA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38108
Abstract
Utilizes a combination of dedicated third metal layer for clock routing and circuit techniques that provides reduced voltage swing buffer, balanced clock tree driver and clock phase delay elimination. An optimal clock distribution can be attained at lower power consumption. Place and route methodology is also described
Keywords
VLSI; buffer circuits; clocks; delays; driver circuits; balanced clock tree driver; circuit techniques; clock distribution scheme; clock phase delay elimination; clock routing; complex IC system; dedicated third metal layer; place-and-route methodology; power consumption; reduced voltage swing buffer; Capacitance; Capacitors; Clocks; Delay; Driver circuits; Energy consumption; Frequency; Low voltage; Routing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242962
Filename
242962
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