Title :
Records of the 2004 International Workshop on Memory Technology, Design and Testing
Abstract :
Presents the cover from the proceedings of this conference.
Keywords :
built-in self test; cache storage; integrated circuit reliability; integrated circuit testing; integrated memory circuits; memory architecture; random-access storage; BISD; BISR; BIST; efficient cache controllers; embedded memory test; fast EEC; industrial practices; magnetic tunnel junction; magnetoresistive random-access memory; memories reliability; memory fault coverage; repair memories; test analysis; test memories;
Conference_Titel :
Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7695-2193-2
DOI :
10.1109/MTDT.2004.1327970
