DocumentCode
3351880
Title
SF-LRU cache replacement algorithm
Author
Alghazo, Jaafar ; Akaaboune, Adil ; Botros, Nazeih
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear
2004
fDate
9-10 Aug. 2004
Firstpage
19
Lastpage
24
Abstract
In this paper we propose a replacement algorithm, SF-LRU (second chance-frequency - least recently used) that combines the LRU (least recently used) and the LFU (least frequently used) using the second chance concept. A comprehensive comparison is made between our algorithm and both LRU and LFU algorithms. Experimental results show that the SF-LRU significantly reduces the number of cache misses compared the other two algorithms. Simulation results show that our algorithm can provide a maximum value of approximately 6.3% improvement in the miss ratio over the LRU algorithm in data cache and approximately 9.3% improvement in miss ratio in instruction cache. This performance improvement is attributed to the fact that our algorithm provides a second chance to the block that may be deleted according to LRU´s rules. This is done by comparing the frequency of the block with the block next to it in the set.
Keywords
cache storage; low-power electronics; LFU; LRU rules; SF-LRU; cache misses reduction; cache replacement algorithm; data cache; instruction cache; low power cache; miss ratio improvement; performance improvement; second chance concept; second chance-frequency - least recently used; Application software; Bridges; Cache memory; Clocks; Costs; Delay; Energy consumption; Frequency; History; System performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on
ISSN
1087-4852
Print_ISBN
0-7695-2193-2
Type
conf
DOI
10.1109/MTDT.2004.1327979
Filename
1327979
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