Design of a Synchronous Rectifier Controller for Limiting Reverse Current

In this paper, a novel reverse current limiting circuit and the relative mechanism are both designed for the controlling loops of a peak-current-mode synchronous buck converter. The formulation and simulation results show that reverse current threshold is adjustable by changing the emitter junction´s area ratio. When applying it to a typical condition of distributed power system (DPS), the efficiency under light load and middle load is 2%~4% up and the transient response from heavy load to light load is improved than that without reverse current limiting circuit.