A high-density 6.9 sq. /spl mu/m embedded SRAM cell in a high-performance 0.25 /spl mu/m-generation CMOS logic technology

Author

Subbanna, S. ; Agnello, P. ; Crabbe, E. ; Schulz, R. ; Wu, S. ; Tallman, K. ; Saccamango, M.J. ; Greco, S. ; McGahay, V. ; Allen, A.J. ; Chen, B. ; Cotler, T. ; Eld, E. ; Lasky, J. ; Ng, H. ; Ray, A. ; Snare, J. ; Su, L. ; Sunderland, D. ; Sun, J. ; Davar

Author_Institution

Semicond. Res. & Dev Center, IBM Microelectron., Hopewell Junction, NY, USA

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

275

Lastpage

278

Abstract

In this work, we demonstrate a 6.9 sq. /spl mu/m embedded SRAM cell in a 0.25 /spl mu/m physical design-rule salicide high-performance CMOS technology. The scalability of this salicide-CMOS embedded-SRAM technology is demonstrated by functionality of the same SRAM cell implemented in 0.35 /spl mu/m and 0.25 /spl mu/m design rules. To our knowledge this is the smallest reported SRAM cell in a salicide-only technology, and is achieved using deep-UV lithography, shallow-trench isolation, damascene tungsten low-resistance local interconnect, and optimization of design-rules. Process and structure studies indicate process extendability to 0.18 /spl mu/m lithography generation. The CMOS technology is a 1.8 V, 0.12 /spl mu/m nominal L/sub EFF/, dual work-function CMOS with 4.0 nm gate oxide. The unloaded inverter and 2-way NAND gate delays are 24 and 45 ps respectively with 1.8 V power supply, and 57 and 98 ps with 1.0 V power supply.

Keywords

CMOS memory circuits; SRAM chips; circuit optimisation; delays; integrated circuit design; integrated circuit interconnections; isolation technology; photolithography; 0.25 mum; 0.35 mum; 1 V; 1.8 V; 2-way NAND gate delay; 24 ps; 4 nm; 45 ps; 57 ps; 98 ps; CMOS logic technology; damascene W low-resistance local interconnect; deep-UV lithography; design-rule optimization; dual work-function CMOS; embedded SRAM cell; gate oxide; physical design-rule; power supply; process extendability; salicide-CMOS embedded-SRAM technology; scalability; shallow-trench isolation; unloaded inverter delay; CMOS logic circuits; CMOS technology; Design optimization; Inverters; Isolation technology; Lithography; Power supplies; Random access memory; Scalability; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.553583

Filename

553583