A graph matching based integrated scheduling framework for clustered VLIW processors

Scheduling for clustered architectures involves spatial concerns (where to schedule) as well as temporal concerns (when to schedule) and various clustered VLIW configurations, connectivity types, and inter-cluster communication models present different performance trade-offs to a scheduler. The scheduler is responsible for resolving the conflicting requirements of exploiting the parallelism offered by the hardware and limiting the communication among clusters to achieve better performance without stretching the overall schedule. This paper proposes a generic graph matching based framework that resolves the phase-ordering and fixedordering problems associated with scheduling on a clustered VLIW processor by simultaneously considering various scheduling alternatives of instructions. We observe approximately 16% and 28% improvement in the performance over an earlier integrated scheme and a phase-decoupled scheme respectively without extra code size penalty.