Radiation tolerant IP Cores for the control and readout of Front-End electronics in High Energy Physics experiments

In future HEP experiments the increased luminosity and the need of higher detector performance will push toward severe requirements on radiation hardness and power dissipation of hardware components. The use of “standard” and flexible protocols, modular architectures and IP-cores available to ASIC and FPGA designers will contribute to meet these requirements, while keeping development and production costs under control. The goal of the FF-LYNX project is the definition of a flexible protocol that allows the use of the same physical serial links and interfaces for the transmission of Timing, Trigger and Control (TTC) signals and Data Acquisition (DAQ). The protocol has been implemented in TX and RX interfaces based on serial electrical links designed as IP Cores. A test chip has been fabricated in the IBM 130nm CMOS technology. The architecture of the test interface and of the test chip will be presented together with preliminary results on area, speed and power consumption. Also the performance in terms of total ionization dose rad-tolerance will be reported.