Digital error correction and calibration of gain non-linearities in a pipelined ADC

The paper presents algorithms that enable digital calibration and digital error correction of gain non-linearities in pipelined analog-to-digital converters. Calibration allows the use of low open loop gain amplifiers in the front-end sample and hold and interstage gain stages at the expense of added digital complexity. Behavioral simulations of a 14 stage, 1.5 bit per stage, pipelined analog-to-digital converter shows an accuracy of 12 bits in the presence of interstage gain errors in all stages and upto 10% third-order non-linearity in the front-end sample and hold and the first stage.