A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC

A 1.8V 8-bit 250Nsample/s Nyquist-rate CMOS pipelined ADC with a 1.5-bit/stage architecture is presented. The proposed gain of half sample-and-hold amplifier (SHA) reduces the power consumption about 40% comparing with a conventional gain of one SHA. This ADC achieves better than 43.2dB SNDR at 250-Msample/s for a 120MHz input frequency. The measured DNL and INL are ±0.55 LSB and ±0.94 LSB, respectively. The ADC fabricated in a 0.18μm CMOS process consumes 279mW from a 1.8V power supply and occupies 2.5mm².