A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter

A pipeline architecture that combines a new radix<2 gain-stage and the traditional 1.5-bit/stage structures is presented. The 10-bit, 60MHz, 3.3-V pipelined analog-to-digital converter has been designed in a 0.25μm 1P4M CMOS technology using digital bit-weight self-calibration for the radix<2 stages, while minimizing the overall number of stages using traditional 1.5-bit/stage. The converter achieves more than 57dB signal-to-noise-and-distortion ratio at 30MHz Nyquist full-scale input from a 3.3-V supply within -40°C to +120°C temperature range in all process corner cases. The third order intermodulation harmonic is better than 68dB. The differential and integral non-linearity of the converter are estimated to be within ±0.3 and ±0.2 LSB, respectively. The 1mm × 0.6mm converter dissipates 35mA at 3.3V.