RTP application and technology options for the sub-45 nm nodes

As device dimensions have reduced to nanometer length scales, rapid thermal processing (RTP) has emerged as the key approach for providing the low thermal budget and ultra-pure process conditions that are essential in advanced fabrication schemes. As further progress in electronic technology becomes increasingly dependent on success in rapid development cycles that include both materials innovations and changes in CMOS device architecture, RTP will play a major role in the story. RTP will contribute in gate-stack engineering, oxidation processes, ultra-shallow junctions, silicide formation, low-k dielectric annealing and in fundamental improvement of thin film properties. As device dimensions are controlled at the atomic scale, the concepts of thermal budget reduction will continue to drive the technology, with reductions in both process times and process temperatures combined with control of a very high purity process gas ambient. The thermal and ambient flexibility of RTP will become even more important as processes are developed and optimized for new gate dielectrics, high-mobility channel designs and metal gates combined with device architecture changes such as multiple-gate transistor designs. As the transistor channel length scales towards the ultimate limit imposed by atomic-scale fluctuations and quantum effects, the need for minimization of parasitic resistance and capacitance will become increasingly dominant in device performance. Here, the most critical requirements are to increase the concentrations of electrically active dopants without inducing excessive diffusion and to reduce contact resistances. These challenges will be met through innovation in RTP that addresses opportunities in materials engineering and in thermal cycle design. Further advances in silicon device technology will ultimately be limited by manufacturing costs. Pressure for manufacturing cycle-time reductions will mean that single-wafer processing technologies, including RTP, will co- ntinue to displace batch processing approaches. The final blow for the batch furnace will come from the transition to even larger wafer sizes, where the planar heating geometry inherent in RTP provides a natural fit to the wafer