Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System

Due to the rising complexity of modern chip designs, the connection of the different on-chip IP cores has become an important issue. To establish communication links between computation nodes either wide busses or fast serial data paths - so called networks on chip (NoC) - are necessary, depending on the application and the chip design. In case of the serial links a variety of different algorithms and topologies are cogitable, which have to be evaluated and tested to find the optimal solution for a given problem. To do this, the NoC can be emulated on a hardware platform based on FPGAs to exploit the flexibility for short turn-around-times and achieve nearly real time conditions by accelerating the test process. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient network on chip (NoC) implementation based on Xilinx Virtex-II FPGAs