A process, voltage, and temperature compensated CMOS constant current reference

In this paper, a CMOS constant current reference over PVT (process, voltage and temperature) variations is presented. The drain current of a MOS device gives the reference current, which is compensated for process variations by exploiting the physical relationship between K´(μC_ox) and V_T across various process corners. It is also compensated for power supply and temperature variations by a PTAT voltage reference, which aids in the generation of the reference current. In order to prove the proposed concept, simulation results from 0.25 μm, 0.18 μm, 0.13 μm, and 90 nm CMOS processes are presented.