Incorporating testability considerations in high-level synthesis

The authors propose an algorithm for module and register binding which generates register-transfer-level (RTL) designs having low testability cost. They also present an algorithm for altering the register and module binding to reduce testability overhead in the final design. These algorithms were coded and several experiments were conducted to check their performance. The results of these experiments are described. The study shows that the designs produced by the method in almost all the cases have reduced testability overhead.<>