Title :
Removal of redundancy in logic circuits under classification of undetectable faults
Author :
Kajihara, S. ; Shiba, H. ; Kinoshita, K.
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
Abstract :
The authors describe a method for removing redundant elements using test pattern generation. Redundancy in combinational circuits can be identified from the existence of undetectable stuck-at faults. By classifying undetectable faults into three categories according to their properties obtained in the test pattern generation process, some redundant elements can be concurrently removed. The method produces an irredundant circuit efficiently by using these properties. An improved procedure for redundancy removal is outlined to reduce the number of repetitions of test generation performed in the process. Some environmental results for ISCAS 85 benchmark circuits are also shown.<>
Keywords :
combinatorial circuits; logic testing; ISCAS 85 benchmark circuits; classification; combinational circuits; logic circuits; redundancy removal; redundant elements; test pattern generation; undetectable faults; undetectable stuck-at faults; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Fault diagnosis; Logic circuits; Performance evaluation; Redundancy; Test pattern generators;
Conference_Titel :
Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on
Conference_Location :
Boston, MA, USA
Print_ISBN :
0-8186-2875-8
DOI :
10.1109/FTCS.1992.243575
