A divide-and-conquer approach to test generation for large synchronous sequential circuits

Author

Pomeranz, I. ; Reddy, S.M.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1992

fDate

8-10 July 1992

Firstpage

230

Lastpage

237

Abstract

A method for generating tests for synchronous sequential circuits that does not use the complete circuit description is proposed, to allow true divide-and-conquer to be applied to test generation. The method is based on the generation of primary input sequences such that for as many sequences generated by the adjacent subcircuits as possible, a test sequence for the subcircuit under consideration would result. Repeated application of test sequences is proposed as a means of increasing the probability of fault detection. Experimental results are presented to show that the method is applicable to subcircuits of large sequential circuits.<>

Keywords

logic testing; sequential circuits; divide-and-conquer approach; large synchronous sequential circuits; primary input sequences; probability of fault detection; test generation; Circuit faults; Circuit testing; Cities and towns; Contracts; Fault detection; Hardware; Performance evaluation; Sequential analysis; Sequential circuits; Synchronous generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on

Conference_Location

Boston, MA, USA

Print_ISBN

0-8186-2875-8

Type

conf

DOI

10.1109/FTCS.1992.243579

Filename

243579