Scheduling with rollback constraints in high-level synthesis of self-recovering ASICs

The authors develop software mechanisms for incorporating on-chip self-recovery-using checkpointing and rollback-during high-level synthesis. They propose an algorithm for rollback point insertion to minimize rollback overhead. It identifies good rollback points by successively eliminating clock cycle boundaries that are either expensive or violate the recovery time constraint. Only the minimum number of rollback points are inserted. A flexible synthesis methodology is presented in which rollback point insertion can precede, succeed, or be intertwined with scheduling. A novel edge-based scheduling algorithm is described that schedules edges to clock cycle boundaries, in addition to scheduling nodes to clock cycles. The system has been used to schedule flow graphs from the literature. Experimental results are presented.<>