Single b-bit byte error correcting and double bit error detecting codes for high-speed memory systems

The authors propose a novel design method for single b-bit byte error correcting and double bit error detecting code, called Sb EC-DED code, suitable for high-speed memory systems using byte organized RAM chips. This type of byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing codes. A code design method using elements from a coset of a subfield under addition gives the practical Sb EC-DED code with 64 information bits and 4-bit byte length which has the same check-bit length, 12 bits, as that of the single byte error correcting code. This also has very high error detection capabilities of random double byte errors and of random triple bit errors.<>