DocumentCode
3354777
Title
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce
Author
Tsung-wei Huang ; Wong, Martin D. F.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear
2015
fDate
6-6 June 2015
Firstpage
1
Lastpage
6
Abstract
Incremental path-based timing analysis (PBA) is a pivotal step in the timing optimization flow. A core building block analyzes the timing path-by-path subject to a critical amount of incremental changes on the design. However, this process in nature demands an extremely high computational complexity and has been a major bottleneck in accelerating timing closure. Therefore, we introduce in this paper a fast and scalable algorithm of incremental PBA with MapReduce - a recently popular programming paradigm in big-data era. Inspired by the spirit of MapReduce, we formulate our problem into tasks that are associated with keys and values and perform massively-parallel map and reduce operations on a distributed system. Experimental results demonstrated that our approach can not only easily analyze huge deisgns in a few minutes, but also quickly revalidate the timing after the incremental changes. Our results are beneficial for speeding up the lengthy design cycle of timing closure.
Keywords
optimisation; parallel processing; timing; MapReduce; PBA; big-data era; building block; distributed system; incremental path-based timing analysis; lengthy design cycle; programming paradigm; timing closure; timing optimization flow; Algorithm design and analysis; Benchmark testing; Optimization; Runtime; Timing; Transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
System Level Interconnect Prediction (SLIP), 2015 ACM/IEEE International Workshop on
Conference_Location
San Francisco, CA
Type
conf
DOI
10.1109/SLIP.2015.7171710
Filename
7171710
Link To Document