DocumentCode :
3354878
Title :
Protecting practical FFT implementations that share common processing elements
Author :
Sung, J. ; Redinbo, R.
Author_Institution :
California Univ., Davis, CA, USA
fYear :
1992
fDate :
8-10 July 1992
Firstpage :
420
Lastpage :
429
Abstract :
Functional faults are discussed. Before any reconfiguration can be done, the error must first be detected and, then, the malfunctioning unit must be identified. Fault detection is considered. The authors assume there is at most one malfunctioning in the processing array at a time. They describe a general method of detecting any fault occurrence, either permanent or transient, in a practical radix-2 N-point discrete Fourier transform system independent of the technology base and for any reasonable interconnection scheme among these PEs. An algorithm-based fault tolerant (ABFT) concurrent error detection (CED) scheme is derived by scheduling all the PEs with certain characteristics. Two fault detection techniques with these attributes are demonstrated. The general use of gain spaces for ABFT CED scheduling is examined.<>
Keywords :
error analysis; fast Fourier transforms; fault location; fault tolerant computing; multiprocessor interconnection networks; FFT implementations; algorithm-based fault tolerant; common processing elements; concurrent error detection; fault detection techniques; fault occurrence; gain spaces; interconnection scheme; malfunctioning unit; processing array; Delay; Discrete Fourier transforms; Fault detection; Fault tolerance; Fourier transforms; Linear systems; Processor scheduling; Protection; Real time systems; Scheduling algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on
Conference_Location :
Boston, MA, USA
Print_ISBN :
0-8186-2875-8
Type :
conf
DOI :
10.1109/FTCS.1992.243593
Filename :
243593
Link To Document :
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