DocumentCode
3355014
Title
Efficient fault-tolerant mesh and hypercube architectures
Author
Bruck, J. ; Cypher, R. ; Ho, C.-T.
Author_Institution
IBM Almaden Res. Center, San Jose, CA, USA
fYear
1992
fDate
8-10 July 1992
Firstpage
162
Lastpage
169
Abstract
The authors present an efficient method for tolerating faults in d-dimensional mesh and hypercube architectures. The approach consists of adding spare processors and communication links so that the resulting architecture can be reconfigured to form the desired mesh or hypercube in the presence of faults. The cost of the fault-tolerant architecture is optimized by adding exactly k spare processors and minimizing the number of links per processor. The results are surprisingly efficient. For example, when the desired architecture is a d-dimensional mesh and k=1, the fault-tolerant architecture has the same maximum degree as the desired architecture and has only one spare processor. Efficient layouts are presented for fault-tolerant two- and three-dimensional meshes, and it is shown that multiplexers and buses can be used to reduce the degree of the fault-tolerant architectures.<>
Keywords
fault tolerant computing; hypercube networks; parallel architectures; buses; communication links; d-dimensional mesh; fault-tolerant mesh; hypercube architectures; layouts; multiplexers; spare processors; Computer architecture; Cost function; Fault tolerance; Hypercubes; Large scale integration; Microprocessors; Multiplexing; Parallel machines; Redundancy; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on
Conference_Location
Boston, MA, USA
Print_ISBN
0-8186-2875-8
Type
conf
DOI
10.1109/FTCS.1992.243604
Filename
243604
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