Design of fully exercised SFS/SCD logic networks

The authors contribute two important design techniques to the realization of a large logic network that effectively achieves the goal of being totally self-checking. A systematic design method is presented for strongly fault-secure (SFS) and strongly code-disjoint (SCD) sequential circuits which can be used as embedded circuits with the inputs having no need to be monitored by any checker. Second, a remapping technique is presented for embedded logic functions of combinational and sequential circuits interconnected in cascade. The technique allows the embedded input interface of each component circuit to be fully exercised in normal operation so that the entire logic network proves to be SFS and SCD.<>