DocumentCode
3355200
Title
Branch recovery with compiler-assisted multiple instruction retry
Author
Alewine, N.J. ; Chen, S.-K. ; Li, C.-C. ; Fuchs, W.K. ; Hwu, W.-M.
Author_Institution
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fYear
1992
fDate
8-10 July 1992
Firstpage
66
Lastpage
73
Abstract
A compiler-assisted approach to implementing multiple instruction retry has recently been developed by C.-C. J Li et al. (1991). They extend compiler-assisted multiple instruction retry to include a broad class of code execution failures. Five benchmarks were used to measure the performance penalty of hazard resolution. Results indicate that the enhanced pure software approach can produce performance penalties consistent with existing hardware techniques. A combined compiler/hardware resolution strategy is also described and was evaluated. Experimental results indicate a lower performance penalty than with either a totally hardware or totally software approach.<>
Keywords
fault tolerant computing; performance evaluation; system recovery; benchmarks; branch recovery; code execution failures; combined compiler/hardware resolution; compiler-assisted multiple instruction retry; hazard resolution; Checkpointing; Computer aided instruction; Counting circuits; Delay; Hardware; Hazards; NASA; Registers; Software performance; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on
Conference_Location
Boston, MA, USA
Print_ISBN
0-8186-2875-8
Type
conf
DOI
10.1109/FTCS.1992.243614
Filename
243614
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