Advanced HiCTE ceramic flip-chipping of 90nm Cu/low-k device: a novel material, package structure, and process optimization study

This study analyzes the effect of the eight metal layer 90nm Cu/low-k flip chip devices through designed experiment using two relatively different underfill materials, standard terminal pad and novel passivation structures, and JEDEC Level-3 reliability stressings (TC, HAST, and HTS). Black diamond low-k and HiCTE ceramic substrate are employed for the large package form-factor. The active Si utilizes eutectic stencil-pasted SnPb bump and BGA balls with Ti/Ni-V/Al-Cu reflectory thin film deposited UBM. It is found that the double passivation pad structures are less susceptible to reliability damages for various types of underfills; although a single passivation with BCB coating combined with an optimal underfill can also yield similar favorable result. The metallurgical effect of delamination cracking, HiCTE flip chip and stress-relieving passivation structures, and underfill interfaces failure mode mechanism are examined by functional testing, chemical deprocesssings, SAM, and SEM/EDX.