Design optimization of a high performance FCAMP package for manufacturability and reliability

There are distinct advantages of using multi-chip modules for leveraging performance. There are also handicapping issues with respect to known good die, test access, and repairability/rework. An FCAMP, or flip chip and memory package, is a way of resolving some of these problems and mitigating yield and reliability risk. The FCAMP allows for a flip chip ASIC die, and packaged, tested at-speed, and burned-in memory components to be assembled onto a substrate. Using direct chip attach for the ASIC reduces the body size of the FCAMP substrate. CSP type of packaged memory allows for full testing prior to assembly. The FCAMP device used in this investigation contains a flip chip die and four custom packaged SRAM. The system is architected so that the bulk of the interconnect resides on the substrate. The challenges of this package are routability with acceptable signal integrity and power integrity, packaging thermal mechanical integrity, package co-planarity, and long term reliability. This paper presents an overall design methodology along with evaluation of materials and substrate selection. The impact of the underfill material selection, SRAM packaging technology, lid material, and lid design on package warpage and manufacturability will be discussed. Preliminary reliability results are presented.