Design and Implementation of Reconfigurable Modulo (2n+1) Multiplication IP Core using FPGAs

Author

Liu, Yuanfeng ; Meng, Qiang ; Dai, Zibin ; Liu, Jianguo

Author_Institution

Inst. of Electron. Technol., Inf. Eng. Univ., ZhengZhou

fYear

2006

fDate

3-5 Aug. 2006

Firstpage

539

Lastpage

542

Abstract

In this paper, a high-performance and dynamic reconfigurable modulo (2ⁿ+l) multiplication IP core is presented, which provides full support to 8/16/32-bits n value. To save the hardware cost, we adopt sharing technique to modulo (2ⁿ+1) multiplication modules based on low-high algorithm. Compared with traditional schemes, the reconfigurable scheme not only provides full hardware support for the modulo (2ⁿ+1) multiplication implementing modes and three possible n value, but also reduces the required logic elements to 5% and he required DSP to 72% on equivalent frequency. This one also provides a better security and flexibility scheme for different requirements

Keywords

field programmable gate arrays; reconfigurable architectures; transport protocols; IP core; Internet protocol; field programmable gate array; hardware cost; logic element; low-high algorithm; reconfigurable modulo multiplication; sharing technique; Adders; Algorithm design and analysis; Costs; Cryptography; Design engineering; Encoding; Field programmable gate arrays; Hardware; Logic devices; Pervasive computing; Low-High algorithm; Ma´algorithm; modulo multiplication; reconfigurable;

fLanguage

English

Publisher

ieee

Conference_Titel

Pervasive Computing and Applications, 2006 1st International Symposium on

Conference_Location

Urumqi

Print_ISBN

1-4244-0326-x

Electronic_ISBN

1-4244-0326-x

Type

conf

DOI

10.1109/SPCA.2006.297478

Filename

4079049