A compensation-based optimization methodology for gain-boosted opamp

A gain-boosted opamp design methodology is presented. The methodology provides a systematic way of gain-boosted opamp optimization in terms of AC response and settling performance. The evolution of the major poles and zeros of the gain-boosted opamp is studied, which reveals the rationale behind our optimization effort. A sample opamp was implemented in 0.6 μm CMOS technology. It achieves a DC gain of 88 dB, a bandwidth of 725 MHz with 49° phase margin and a 0.1% settling time of 4.5 ns. The sample/hold front-end of a 12-bit 50 MSample/s ADC was implemented with this opamp. It achieves an SNR of 78 dB for an 8.1 MHz input signal.