DocumentCode
3355630
Title
A system level synthesis framework for computer architectures
Author
Tanir, Oryal ; Agarwal, V.K. ; Bhatt, P.C.P.
Author_Institution
MACS Lab., McGill Univ., Montreal, Que., Canada
fYear
1992
fDate
23-25 Jun 1992
Firstpage
94
Lastpage
111
Abstract
A framework for system level synthesis is presented, and a suitable language, DSL, for capturing design specifications and generating control graphs amiable to synthesis is proposed. The three stages in the synthesis process-design specification, intermediate representation, and synthesis-are examined in detail. A rough version of the language is used to model a simple system
Keywords
Petri nets; computer architecture; formal specification; specification languages; DSL; Petri nets; computer architectures; control graphs; design specifications; specification language; system level synthesis framework; Chip scale packaging; Computer architecture; Control system synthesis; Design automation; Digital systems; Laboratories; Logic design; Logic gates; Network synthesis; Terminology;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 1992. Shortening the Path from Specification to Prototype, 1992 International Workshop on
Conference_Location
Research Triangle Park, NC
Print_ISBN
0-8186-3520-7
Type
conf
DOI
10.1109/IWRSP.1992.243914
Filename
243914
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