A precise CMOS mismatch model for analog design from weak to strong inversion

A five parameter mismatch model continuous from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region by Serrano-Gotarredona and Linares-Barranco (1999). A mismatch characterization of NMOS and PMOS transistors for 30 different geometries has been done with this continuous model. The model is able to predict current mismatch with a mean relative error of 13.5% in the weak inversion region and 5% in strong inversion. This is verified for 12 different curves, sweeping V_G, V_DS, V_S. Since data is available for 30 different sizes, the mismatch model can be expressed as a function of transistor width W and L, independently. The proposed model, with explicit W and L dependency has been implemented in the Spectre simulator. Simulations reveal that such precise modeling of mismatch (with explicit W and L dependency) can improve analog circuit performance without penalty on power and area consumption: just by splitting transistors into the optimum number of segments.