Title :
A wide-range and fast-locking clock synthesizer IP based on delay-locked loop
Author :
Hwang, Chorng-Sii ; Chen, Poki ; Tsao, Hen-Wai
Author_Institution :
Dept. of Electr. Eng. & Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
Abstract :
A wide-range and fast-locking clock synthesizer IP based on delay-locked loop is proposed. The ROSC-type cyclic delay line is employed for clock generation. A frequency detector is designed to provide fast-locking capability and the frequency switching behavior like the traditional PLL-based clock synthesizer. This design also includes initial start-up circuitry to activate the whole system from unlimited delay. The proposed clock synthesizer can solve the problem of changing frequency comparing to the conventional DLL-based clock synthesizers. Simulation results show that the output frequency range can operate from 10 to 500 MHz. the HSPICE simulation results are based upon TSMC 0.35μm 2P4M CMOS process with a 3.3V power supply voltage. The power is less than 30mW at the highest output frequency. The core area for the design is 0.095mm2.
Keywords :
CMOS integrated circuits; clocks; delay lines; delay lock loops; frequency synthesizers; phase detectors; 0.35 micron; 10 to 500 MHz; 3.3 V; HSPICE simulation; ROSC-type cyclic delay line; TSMC 2P4M CMOS process; clock generation; delay-locked loop; fast-locking capability; fast-locking clock synthesizer IP; frequency detector; frequency switching behavior; phase locked loop; wide-range clock synthesizer IP; Circuit simulation; Clocks; Delay lines; Delay systems; Detectors; Frequency synchronization; Frequency synthesizers; Logic; Pulse generation; Timing;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328312
