Low-k fluorinated amorphous carbon interlayer technology for quarter micron devices

Author

Matsubara, Y. ; Endo, K. ; Tatsumi, T. ; Ueno, H. ; Sugai, K. ; Horiuchi, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

369

Lastpage

372

Abstract

We have developed a new interlayer technology that attains a 50% reduction in capacitance and keeps good process compatibility with current Chemical Mechanical Polishing (CMP) based multi-level metallization (MLM) processes. This technology uses fluorinated amorphous carbon (a-C:F) with a dielectric constant of 2.3, sandwiched between layers of SiO/sub 2/, which are formed sequentially by high density plasma-chemical vapor deposition (HDP-CVD). The top SiO/sub 2/ layer assures oxygen plasma resistance during via etching, metal etching, and resist removal.

Keywords

adhesion; capacitance; carbon; dielectric thin films; fluorine; integrated circuit metallisation; permittivity; plasma CVD; polishing; sputter etching; 0.25 mum; Al; O plasma resistance; SiO/sub 2/ layers; SiO/sub 2/-C:F-SiO/sub 2/; capacitance reduction; chemical mechanical polishing based multi-level metallization processes; dielectric constant; high density plasma-chemical vapor deposition; low-k amorphous C:F interlayer technology; metal etching; process compatibility; quarter micron devices; resist removal; via etching; Amorphous materials; Capacitance; Chemical processes; Chemical technology; Dielectric constant; Etching; Metallization; Plasma applications; Plasma chemistry; Plasma density;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.553605

Filename

553605