Experimental testing and computational stress analysis of printed circuit board for the failure prediction of passive components under the depaneling load condition

Nowadays, the trend of microelectronic devices is to achieve more functions but with smaller sizes: In order to fulfill this requirement, not only the density of packaging needs to be increased, but also the sizes of components have to be decreased. Due to the reduction of sizes, the electronic components may become more and more susceptible to the loading induced from various fabrication processes. Depaneling of printed circuit boards is quite common at the end of the manufacturing of microelectronic systems in order to singulate each individual unit. It is found that, if the boards are under a certain mechanical loading, the risk of cracking the tiny passive components is high. The present study is intended to establish a model for the failure prediction of passive components under the depaneling load condition. Both experimental testing and computational stress analysis are performed. The testing part is for the purpose of measuring depaneling load and board strains to validate the computational model. The computational stress analysis is performed with a 3D finite element model. The emphasis is placed on finding the correlation between the bending strain on the PCB (which is an index of the local curvature of the bent PCB) and the bending stress in the passive components (which is the reason to crack chip capacitors/resistors). It is observed that such a relationship can be established. With this model, the cracking of passive components may be predicted under the depaneling load condition. The understanding of this potential threat can be turned into a design rule to avoid mounting passive components in the "high risk" area on the PCB. As a result, the objective of "design for reliability" can be achieved.