X-MatchPRO: a high performance full-duplex lossless data compressor on a ProASIC FPGA

Author

Núñez, José Luis ; Jones, Simon ; Bateman, Stephen

Author_Institution

Electron. Syst. Design Group, Loughborough Univ. of Technol., UK

fYear

2001

fDate

2001

Firstpage

56

Lastpage

60

Abstract

This paper presents the full-duplex architecture of the X-MatchPRO lossless data compressor and its highly integrated implementation in a non-volatile reprogrammable ProASIC FPGA. The X-MatchPRO architecture offers a data independent throughput of 100 Mbytes/s and simultaneous compression/decompression for a combine full duplex performance of 200 Mbytes/s clocking at 25 MHz. Both compression and decompression channels fit into a single A500K130 ProASIC FPGA with a typical compression ratio that halves the original uncompressed data. This device is specifically targeted to enhance the performance of Gbit/s data networks and storage applications where it can double the performance of the original system

Keywords

application specific integrated circuits; data compression; field programmable gate arrays; 100 Mbyte/s; 200 Mbyte/s; 25 MHz; ProASIC FPGA; X-MatchPRO; data compression; data decompression; full-duplex lossless data compressor; nonvolatile reprogrammable FPGA; storage applications; Bandwidth; Clocks; Data compression; Dictionaries; Energy consumption; Field programmable gate arrays; Hard disks; Performance loss; Throughput; Video on demand;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, International Workshop on, 2001.

Conference_Location

Crimea

Print_ISBN

0-7803-7164-X

Type

conf

DOI

10.1109/IDAACS.2001.941979

Filename

941979