A minimization of the charge injection in switched-current circuits

This work provides a new approach to a minimization of the charge injection in switched-current (SI) circuits. This approach aims at minimizing the charge to be injected during MOS switching, instead of reducing the effect of the charge injection, and is very effective and efficient over a wide range of the input current of which the lowest is in a sub-nA level. The implementation of the approach is very easy, and does not require any special fabrication process, area-consuming components, matching devices, and complex clocks. The work can lead to significant improvement of the operation quality of SI circuits without sacrificing speed and power dissipation.