1.2V low-power four-quadrant CMOS transconductance multiplier operating in saturation region

The paper describes a simple CMOS technique for realizing a linear, low-voltage, low-power, four-quadrant transconductance multiplier based on MOS transistors working in saturation region. The proposed circuit has been developed and simulated using standard 0.35μm AMS process. SPICE simulations show that the total harmonic distortion (THD) at 0.3V_pp@1MHz applied to Y input is -70.5dB with 0.1V DC voltage applied to X input. Input referred noise equals 0.6μV/Hz¹2/ which results in the dynamic range of the circuit equal to 52dB. Power consumption is 0.05mW from a single 1.2V supply. An example of application the CMOS multiplier as a modulator is presented.