DocumentCode
3357878
Title
Design of SPWM inverter IP core based on SOPC
Author
Wang, Meng ; Chen, Lin
Author_Institution
Coll. of Inf. Sci. & Eng., Wuhan Univ. of Sci. & Technol., Wuhan, China
fYear
2010
fDate
26-28 June 2010
Firstpage
5864
Lastpage
5867
Abstract
Based on FPGA and SOPC, IP core of pulse width modulation technique is studied in this paper. According to the principle of sinudoidal PWM by natural sampling, using VHDL and macro functions module design method, the design of PWM IP core on FPGA is achieved. Switching frequency and dead time are programmable. The functions of the IP core are simulated and tested. The results of simulation and experiment are shown.
Keywords
field programmable gate arrays; hardware description languages; industrial property; logic design; system-on-chip; FPGA; SOPC; SPWM inverter IP core design; VHDL; macro functions module design method; natural sampling; sinudoidal pulse width modulation; switching frequency; Design engineering; Design methodology; Educational institutions; Field programmable gate arrays; Information science; Pulse inverters; Pulse width modulation; Pulse width modulation inverters; Read only memory; Sampling methods; FPGA; IP core; SOPC; SPWM;
fLanguage
English
Publisher
ieee
Conference_Titel
Mechanic Automation and Control Engineering (MACE), 2010 International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-7737-1
Type
conf
DOI
10.1109/MACE.2010.5536144
Filename
5536144
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