High-level design environment for massive parallel VLSI-implementations of statistical signal- and image processing models

In this paper we introduce and describe a generic and semiconductor-technology independent hardware development environment for a class of statistical signal- and image processing models. The statistical signal- and image processing approach under consideration formally adopts the Bayesian paradigm and uses discrete Markov random field (MRF) models for the processing models to derive the joint distribution of signal- and image processing problems by means of mathematically and computationally tractable conditional distributions. We experimentally demonstrate and prove the capabilities respectively the concepts of the proposed high-level design environment by detailed chip layouts of different neighbourhood topologies and a single processing element of a MRF-architecture, which solves the image processing problem of noise removing, restoration and intensity-level preserving.