Title :
Space-saving layout for passive components
Author :
Karjalainen, P.H. ; Heino, P.
Author_Institution :
Inst. of Electron., Tampere Univ. of Technol., Finland
Abstract :
The large number of passive components in mobile electronics devices require a large area. In this study, the passive components on the test chip are processed using a commercial CMOS process. The layout area is reduced by superimposing the on-wafer passive components of the basic inductor-capacitor and inductor-resistor circuits. The resonant frequency of the LC circuit using the stacked components matches well with the calculated value of the reference components. The effect of the parasitic components between the stacked passive components is found negligible in the operating frequency range.
Keywords :
CMOS integrated circuits; integrated circuit layout; CMOS process; LC circuit; inductor-capacitor circuits; inductor-resistor circuits; mobile electronics devices; on-wafer passive components; resonant frequency; space-saving layout; Analog circuits; CMOS process; Capacitors; Circuit testing; Economics; High K dielectric materials; Inductors; RLC circuits; Resonant frequency; Space technology;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.84
