DocumentCode
3358645
Title
High-performance noise-robust asynchronous circuits
Author
Golani, P. ; Beerel, P.A.
Author_Institution
Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA
fYear
2006
fDate
2-3 March 2006
Abstract
This paper presents the development of a prototype high-performance asynchronous standard-cell library based on the static single-track full buffer family. It focuses on the design choices and challenges that mitigate sensitiveness to noise, including transistor sizing and wire spacing rules. Post-layout simulation results demonstrate its robustness to noise while achieving a peak cycle time of 5.7 FO4 delays
Keywords
asynchronous circuits; buffer circuits; circuit noise; logic design; asynchronous circuits; buffer circuits; single-track full buffer family; transistor sizing rules; wire spacing rules; Asynchronous circuits; Circuit noise; Circuit simulation; Crosstalk; Libraries; Noise robustness; Pipelines; Prototypes; Wires; Working environment noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location
Karlsruhe
Print_ISBN
0-7695-2533-4
Type
conf
DOI
10.1109/ISVLSI.2006.51
Filename
1602436
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