Title :
High-performance noise-robust asynchronous circuits
Author :
Golani, P. ; Beerel, P.A.
Author_Institution :
Dept. of Electr. Eng.-Syst., Southern California Univ., Los Angeles, CA
Abstract :
This paper presents the development of a prototype high-performance asynchronous standard-cell library based on the static single-track full buffer family. It focuses on the design choices and challenges that mitigate sensitiveness to noise, including transistor sizing and wire spacing rules. Post-layout simulation results demonstrate its robustness to noise while achieving a peak cycle time of 5.7 FO4 delays
Keywords :
asynchronous circuits; buffer circuits; circuit noise; logic design; asynchronous circuits; buffer circuits; single-track full buffer family; transistor sizing rules; wire spacing rules; Asynchronous circuits; Circuit noise; Circuit simulation; Crosstalk; Libraries; Noise robustness; Pipelines; Prototypes; Wires; Working environment noise;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.51
