Mismatch analysis and statistical design at 65 nm and below

Transistor sizing to control random mismatch is investigated. Input offset voltage of 65 nm bulk CMOS SRAM sense amplifiers are measured to analyze NMOS and PMOS threshold voltage (Vtn, Vtp) variation effects and compare them with statistical models and Pelgrom model predictions. A linear statistical response surface model (RSM) relating input offset to Vtn and Vtp is shown to agree well with measured results. Designs optimized using the RSMs produce circuits with 25% lower input offset voltage spread at a cost of 10% more active device area. Statistical models for post-manufacturing configuration are postulated and shown for sub-65 nm technologies.