Title :
A 90–240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking
Author :
Li, Pengfei ; Bhatia, Deepak ; Xue, Lin ; Bashirullah, Rizwan
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL
Abstract :
This paper reports a digital phase locked loop (DPLL) frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed technique achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a wide range of parameters and can be locked to a reference clock to ensure the converter switching frequency falls outside power supply resonance bands. We demonstrate a 90-240 MHz single phase converter with fast hysteretic control and output conversion range of 33%-80%. The converter achieves an efficiency of 80% at 180 MHz, a load response of 40 ns for a 120 mA current step and a peak-to-peak ripple less than 25 mV. The circuit was implemented in 130 nm digital CMOS process.
Keywords :
CMOS digital integrated circuits; DC-DC power convertors; digital phase locked loops; hysteresis; digital CMOS process; digital PLL frequency locking; digital phase locked loop; frequency 90 MHz to 240 MHz; hysteretic controlled DC-DC buck converter; reference clock; size 130 nm; switching frequency; Buck converters; Clocks; Frequency conversion; Frequency locked loops; Hysteresis; Phase locked loops; Power supplies; Switching converters; Switching frequency; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672010