Title :
Complexity and low power issues for on-chip interconnections in MPSoC system level design
Author :
Sheynin, Y. ; Suvorova, E. ; Shutenko, F.
Author_Institution :
St. Petersburg State Univ. of Aerosp. Instrum., Russia
Abstract :
System level design for many-core chips includes general system architecture design, MPSoC design as a set of nodes and their interconnection. It requires adequate models and methodology to estimate MPSoC interconnection characteristics in complexity and power consumption to make decisions at the system level design stage of an MPSoC project. To determine performance and power consumption of MPSoC we suggest the simplified model of tentative wires for evaluating interconnection topology at early stages of design process, to correspond them with technology characteristics, with power dissipation and power consumption. With this approach we reason about many-core SoC interconnections, place and route, methodology for system level design of MPSoC interconnections.
Keywords :
integrated circuit design; integrated circuit interconnections; low-power electronics; multiprocessor interconnection networks; system-on-chip; MPSoC interconnection; MPSoC interconnections; MPSoC system level design; general system architecture design; interconnection topology; on-chip interconnections; Chip scale packaging; Delay; Energy consumption; Integrated circuit interconnections; Power dissipation; Power system interconnection; Power system modeling; System-level design; System-on-a-chip; Topology;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.30
