Complexity and low power issues for on-chip interconnections in MPSoC system level design

System level design for many-core chips includes general system architecture design, MPSoC design as a set of nodes and their interconnection. It requires adequate models and methodology to estimate MPSoC interconnection characteristics in complexity and power consumption to make decisions at the system level design stage of an MPSoC project. To determine performance and power consumption of MPSoC we suggest the simplified model of tentative wires for evaluating interconnection topology at early stages of design process, to correspond them with technology characteristics, with power dissipation and power consumption. With this approach we reason about many-core SoC interconnections, place and route, methodology for system level design of MPSoC interconnections.